A. Technical Field
The present invention relates to a method for computer signal processing, and more particularly, to a method for providing data communication between a firmware controller and a host processor or Basic Input/Output System (BIOS) on a Peripheral Component Interconnect (PCI) Bus.
B. Background of the Invention
A host processor communicates with various peripheral devices to control the operation of these devices within the processor's system. One such example is a processor communicating with a memory device, such as a redundant array of independent disks (“RAID”), via a PCI Bus. Typically, this communication between the host processor and memory device occurs in fixed frame length command blocks on the PCI Bus. For example, communication between a firmware controller and a host processor may occur in fixed eight frame length command blocks. The command blocks communicate instructions from the host processor to an agent device's controller. This controller may operate within the device firmware and operate as an input/output processor for the device.
As the number of peripherals increases and/or the size of commands from the host processor increases, the PCI Bus may become overburdened. This stress on the PCI Bus may reduce the overall performance of the host system as well as peripherals communicating on the PCI Bus. One potential cause for stressing a PCI Bus is communication between a host processor and RAID firmware.
Communication commands may operate over various different mechanisms. For example, these mechanisms may include message registers, doorbell registers, circular queues, and index registers that allow a host processor or external PCI agent and the firmware controller to communicate through message passing and interrupt generation.
One implementation of an interface between RAID firmware and a host processor is a serialized mailbox, where the driver waits for a “BusyByte” to free before it sends any command to the firmware. The mailbox is basically a fixed length array. Usually, the mailbox is adequate for single-processor systems. However, when a multi-processor system is used, the mailbox may become inadequate and stress the PCI Bus as well as introduce various timing problems between various processors within the system. The message registers generally have four 32-bit registers. Any message, which is a 32-bit data value, is passed in one of the four 32-bit registers. Each written word generates an interrupt, whose flag is cleared before writing another word, thereby passing only single words. This protocol makes the message registers unsuitable for use as head and tail pointer registers.
Circular queues support a message-passing scheme that may use four circular queues. Once again, the message passed in a circular qeue is in a fixed length format. A result of the circular queue is that the host processor can only read or write one word at a time. Additionally, the host processor cannot see the head and tail pointers so it is unable to determine how much space remains. Further, the circular queue is typically used for passing identifiers (addresses or indices) of message buffers with the message bodies being stored elsewhere.
The length of commands, and corresponding required number of frames, changes relative to which commands are communicated. If this communication is between the host processor and a RAID memory device, these frames are fixed in length which may result in empty frames on the PCI bus if a command does not require the total number of frames in the fixed length command block. These wasted empty frames may congest the PCI bus potentially reducing the performance of peripherals attached to the bus.
Accordingly it is desirable to provide a device and method that addresses the above-described problems.